1. Field of the Invention
This invention relates to an apparatus for the parallel processing of data. More particularly, the invention relates to a data parallel processing apparatus well-suited for application to an image processing system in which image data are processed at high speed and in parallel fashion by control of an image memory.
2. Related Art
When an image is processed at high speed, the general approach is to rely upon computer processing using software. However, higher processing speeds are required to deal with larger quantities of image data. There are two methods which can be adopted to raise processing speed. One is to rely upon sequential processing-type hardware or a so-called "pipeline" system. The other is to employ a parallel processing-type system in which a plurality of processors are arranged in parallel fashion. There is a limitation upon the image processing speed achievable with the former system since the clock frequency necessary for processing rises with an increase in the speed at which the picture data are processed. With the latter system, on the other hand, processing speed can be raised as much as desired by increasing the number of processors that are connected in parallel. In fact, speed can be maximized by providing a number of processors equivalent to the number of pixels. For this reason, the latter system represents a technique which is now the focus of much interest.
Here processing for communication between pixels takes on importance and it is necessary that processing proceed while such cross-communication is taking place. In the aforementioned parallel processing system, providing a number of processors equivalent to the number of pixels is impossible when dealing with high-resolution data. For example, when dealing with an image wherein a sheet of A4 size paper is read at 16 pixels/mm, the number of pixels is about 16M, and it would not be feasible to provide the system with this many processors simultaneously.
Accordingly, it is necessary to execute parallel processing using a finite, small number of processors. The specification of U.S. Ser. No. 807,662, filed on Dec. 11, 1985, proposes a technique for accomplishing such parallel processing, which involves dividing image data into a plurality of blocks each comprising plural items of image data, and processing the image data in each block by a respective one of a plurality of CPUs. The arrangement is such that each CPU receives an input of image data of the corresponding block as well as an input of image data of the adjoining blocks, and such that the CPU processes the image data of the corresponding block.
The proposed system still leaves room for improvement in terms of performance and construction.